1. Field of the Invention
The present invention relates to a semiconductor memory device and method of fabricating the same. More particularly, the present invention relates to a non-volatile flash memory device having at least two different channel concentrations and a method of fabricating the same.
2. Description of Related Art
A feature of non-volatile memory devices is that previous data are maintained even when power is not supplied, unlike volatile memory devices. Recently, non-volatile memories such as a ferroelectric random access memory (FRAM), an erasable and programmable read only memory (EPROM), and electrically erasable and programmable read only memory (EEPROM) have been publicized. EPROM and EEPROM store charges on a floating gate store memorize data according to a variation of a threshold voltage depending on whether or not the charges exist. The EEPROM, which is a type of flash memory, erases data in the entire memory cell array or divides the memory cell array into blocks and erases the data in blocks. Non-volatile memory devices such as flash memories are widely used in file systems, memory cards, portable devices, and other applications.
A flash memory cell is divided into two types: a floating gate type and a floating trap type. A polysilicon-oxide-nitride-oxide-silicon (SONOS) structure is well known as a floating trap type device.
A floating gate type device includes a mechanism that stores charges on a floating gate, whereas a SONOS device includes a mechanism that stores charges in traps in a silicon nitride layer. The floating gate type device has a limitation in reducing a cell size and has to use a high voltage for programming and erasing. The SONOS device, however, may satisfy a demand for low power and low voltage and achieve high integration.
FIG. 1A illustrates a cross-sectional view of a conventional non-volatile flash memory device. FIG. 1B is a graph showing a variation of threshold voltage depending on program and erase operations of the conventional non-volatile flash memory device shown in FIG. 1A.
Referring to FIG. 1A, an isolation layer 12, which defines an active region, is disposed on a semiconductor substrate 10. Source and drain regions 35, which are separated by a channel region 17, are disposed in the active region. The channel region 17 includes a first region L1 and a second region L2. A tunneling layer 20, a charge trap layer 22, and a shielding layer 30a are disposed on the first region L1. A gate insulating layer 30b is disposed on the second region L2. The shielding layer 30a and the gate insulating layer 30b are simultaneously formed of the same material layer and are connected. A gate electrode 32 covers both the shielding layer 30a and the gate insulating layer 30b. 
Referring to FIG. 1B, an x-axis denotes a gate length Lgate of the conventional non-volatile flash memory device of FIG. 1A, and a y-axis denotes a threshold voltage Vth. In order to program the non-volatile flash memory device of FIG. 1A, electrons pass through the tunneling layer 20 by a channel-hot electron injection (CHEI) mechanism or a Fowler-Nordheim (FN) tunneling mechanism and are trapped in the charge trap layer 22. A threshold voltage Vth in the first region L1 increases due to the trapped charges. The non-volatile flash memory device varies in threshold voltage according to an amount of trapped electrons and has an “on” level or an “off” level according to a variation of the threshold voltage.
During an erase operation, the trapped electrons are detrapped by a hot hole injection mechanism. Thus, a threshold voltage in the first region L1 decreases. However, the second region L2 has a fixed threshold voltage due to the gate insulating layer 30b. Thus, a sensing margin during program and erase operations is determined by a variation SM1 of the threshold voltage, as shown in FIG. 1B. When a threshold voltage in the second region L2 is reduced by ΔVth, the sensing margin increases, i.e., SM2. One method of reducing the threshold voltage in the second region L2 is to reduce a thickness of the gate insulating layer 30b. However, since the gate insulating layer 30b is formed at the same time as the shielding layer 30a, reducing the thickness of the shielding layer 30a deteriorates cell retention characteristics. Thus, there is a need for research into reducing the threshold voltage in the second region L2 while maintaining the thickness of the gate insulating layer 30b. 